Some conventional copper electroplating processes use additives in the electroplating bath to achieve electrodeposition of the copper with a smooth or level top surface. For example, these conventional processes may be used in printed circuit board fabrication to achieve copper deposits of uniform thickness across the surface of the circuit board, to level or increase the smoothness of the copper deposit, and to increase the rate at which copper deposits inside hole and vias in the circuit board (relative to the surface). Use of these additives allows consistent electrical and mechanical properties of the copper to be achieved across the circuit board's surface.
These conventional processes typically perform the copper electrodeposition from acid sulfate solutions with certain organic additives. For example, additives such as Selrex CuBath M.RTM. and Learonal Copper Gleam are commonly used. These organic additives help achieve the level top surface by increasing the deposition rate of the copper at the lower points of the deposition surface relative to the upper points on the deposition surface. It is believed that the mechanism for this leveling effect is that (a) the organic additives tend to absorb on to the plating surface, thus inhibiting the deposition of copper at the point of absorption, and (b) the mass transfer rate of the organic additives tend to be greater for higher points on the plating surface compared to the lower points on the plating surface. Consequently, the deposition rate at the lower points on the plating surface tends to be greater than the deposition rate at the higher points on the surface. This difference in deposition rate helps to achieve deposition with a level top surface.
However, the inventors have observed that these conventional organic additives are only marginally effective when the plating surface contains very small features (i.e., sub-micron) with high aspect ratios. In particular, the copper fill in a small feature tends to have voids, as shown in FIG. 1. These voids may increase the resistance of (or even open circuit) the conductive path intended to be formed by the copper deposited in the feature. This problem becomes critical in applying copper electrodeposition processes in integrated circuit fabrication. For example, contact and via holes in an integrated circuit can be a quarter micron or less in width, with an aspect ratio of up to four-to-one or greater. In particular, voids in the contacts and vias may result in high resistance interconnects or even open-circuits.
Accordingly, there is a need for an electroplating system capable of filling, without voids, sub-micron high aspect ratio features in a plating surface.